November 8 @ 09:00 - November 9 @ 12:10 CETFree
SYCL is a C++ abstraction layer for programming heterogeneous hardware with a single-source approach. SYCL is high-level, cross-platform, and extends standard ISO C++17. You will learn to:
- Use the hipSYCL compiler to generate executable for multiple hardware targets.
- Write hardware-agnostic code to express parallelism using the queue, command group, and kernel abstractions.
- Use buffer and accessors to handle memory across devices.
- Evaluate drawbacks and advantages of unified shared memory.
The training will run on the EuroHPC JU Vega system. For VEGA specs and other details, visit https://doc.vega.izum.si.
Day 1 – Monday 8 November 2021
Day 2 – Tuesday 9 November 2021
To register for the workshop please follow this link https://events.prace-ri.eu/event/1257/registrations/923/.